yosys-f4pga-plugins
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Published
20 hours ago •
chipsalliance
chipsalliance
ql-qlf plugins: `-no_adder` flag affects cell parameters in output blif
From this section: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/77fb7b17d96d9d5b1fcfb96711f4787cbf26bc4a/ql-qlf-plugin/synth_quicklogic.cc#L535
The logic is causing the cell parameters in output blif to not be written if -no_adder flag is passed in to synth_quicklogic.
We are not sure of the reason behind this logic.
Should this logic be removed to always pass the cell parameters to blif?
This affects RAM scenarios, where the MODE_BITS are not appearing in the output blif, in case the -no_adder is set.
