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Published 20 hours ago • verified publisher icon chipsalliance

Fix issues with QLF_K6N10 cells_sim.v and dsp_sim.v

Open coolbreeze413 opened this issue 2 years ago • 2 comments

This PR has fixes for issues seen while simulating designs with the QLF_K6N10 device.

The major changes are:

  • add specify blocks
  • add missing signals in dsp blocks to avoid warnings
  • add modules LUT_K, fpga_interconnect
  • add explicit wire type declarations for inputs

coolbreeze413 avatar Aug 23 '22 21:08 coolbreeze413

@mkurc-ant could someone review this PR and merge?

tpagarani avatar Aug 31 '22 17:08 tpagarani

@mkurc-ant I will discuss these changes and update.

coolbreeze413 avatar Sep 01 '22 09:09 coolbreeze413

@mkurc-ant I have done the following changes:

  1. Reverted the cells_sim to original version
  2. Created primitives_sim.v file with post-layout macros and respective specify blocks
  3. Made changes that you specified in the dsp_sim.v file

rakeshm75 avatar Nov 11 '22 11:11 rakeshm75

@rakeshm75 Alright, Looks good. Could you please rebase it on top of the main branch? I see that there are conflicts.

mkurc-ant avatar Nov 14 '22 08:11 mkurc-ant

@mkurc-ant The CI issues are resolved, now you can merge.

rakeshm75 avatar Nov 15 '22 16:11 rakeshm75