clash-compiler

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missing: * `~ARGN` * `~INDEXTYPE` * `~MAXINDEX` * `~OTHERSYN` * `~SEL` * `~ISACTIVEHIGH` * `~ISUNDEFINED` * `~STRCMP` * `~OUTPUTUSAGE` (previously named `~OUTPUTWIREREG`) * `~CTXNAME` * `~LONGESTPERIOD`

leonschoorl

Vivado test infrastructure fails on Parameters

7

``` ERROR: [XSIM 43-3225] Cannot find design unit topEntity.testBench in library work located at xsim.dir/work. ``` It seems to try to simulate `topEntity.testBench` instead of `testBench.testBench`, see https://github.com/clash-lang/clash-compiler/pull/2257#issuecomment-1172957230

vmchale

Browsing through the docs for `clash-prelude` before I had a thought: it would be nice to pick some jargon to disambiguate the following: * code which is translatable to HDL,...

alex-mckenna

Memory files in Vivado

1

Vivado test fail on `RomFile`: https://github.com/clash-lang/clash-compiler/pull/2257#issuecomment-1173154137 We can do something more sophisticated in our Vivado tests to get this working: https://github.com/clash-lang/clash-compiler/pull/2257#issuecomment-1173159368

vmchale

Partially fix topological sort of files

1

We don't track dependency information for include files and memory files. Include files are generated from `Clash.Netlist.BlackBox.Types.bbIncludes` or YAML/JSON `includes` keys, and memory files are generated from `~TEMPLATE` holes in...

DigitalBrains1

Vivado test trips up on AndSpecificEnable

1

It gives the following result: ``` Error: outputVerifier, expected: 000000010000000100000001, actual: 000000010000000000000000 Time: 40 ns Iteration: 1 Process: /testBench/r_assert/line__245 File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl Error: outputVerifier, expected: 000000110000001000000010, actual: 000000110000000100000001 Time: 60 ns...

vmchale

Vivado test trips up on BlobVec

1

It gives different results in simulation: ``` Error: outputVerifier, expected: 000000000000000100010000, actual: 000000000001000000100000 Time: 10 ns Iteration: 1 Process: /testBench/r_assert/line__194 File: /tmp/clash-test-e6fd091d2363ea54/BlobVec.testBench/testBench.vhdl Error: outputVerifier, expected: 000000000000000100010000, actual: 000000000001000000100000 Time: 20...

vmchale

We can't simulate in Vivado: ``` ERROR: [XSIM 43-4287] "/tmp/clash-test-5711c4217d9c0815/I2Ctest.I2CConfig.config/configi2c.v" Line 400. Undefined system task '$finish_and_return' ```

vmchale

Right now, the test suite takes e.g. `PortProductsSum_testBench` as an argument to `BuildSpecific`. That makes it needlessly complicated to find the `clash-manifest.json` for a particular entity (here, `verilog/PortProductsSum.topEntity/clash-manifest.json`). We should...

vmchale

Vivado's `mod` misbheaves on negative dividend

1

```haskell import Clash.Prelude import Clash.Explicit.Testbench import Data.Int (Int8) topEntity :: (Int8, Int8) -> Int8 topEntity = uncurry mod {-# NOINLINE topEntity #-} testBench :: Signal System Bool testBench = done...

martijnbastiaan