Vivado test trips up on AndSpecificEnable

[vmchale]

It gives the following result:

                Error: outputVerifier, expected: 000000010000000100000001, actual: 000000010000000000000000
                Time: 40 ns  Iteration: 1  Process: /testBench/r_assert/line__245  File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl
                Error: outputVerifier, expected: 000000110000001000000010, actual: 000000110000000100000001
                Time: 60 ns  Iteration: 1  Process: /testBench/r_assert/line__245  File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl
                Error: outputVerifier, expected: 000001110000010000000100, actual: 000001110000001000000010
                Time: 100 ns  Iteration: 1  Process: /testBench/r_assert/line__245  File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl
                Error: outputVerifier, expected: 000010010000010100000100, actual: 000010010000010000000100
                Time: 120 ns  Iteration: 1  Process: /testBench/r_assert/line__245  File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl
                Error: outputVerifier, expected: 000010110000011000000110, actual: 000010110000010100000100
                Time: 140 ns  Iteration: 1  Process: /testBench/r_assert/line__245  File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl
                Error: outputVerifier, expected: 000011110000100000001000, actual: 000011110000011000000110
                Time: 180 ns  Iteration: 1  Process: /testBench/r_assert/line__245  File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl
                Error: outputVerifier, expected: 00010001UUUUUUUU0UUUUUUU, actual: 000100010000100000001000
                Time: 200 ns  Iteration: 1  Process: /testBench/r_assert/line__245  File: /tmp/clash-test-a14a5f544b110810/AndSpecificEnable.testBench/testBench.vhdl

Perhaps this is a bug in our test infrastructure.

[DigitalBrains1]

Ah it might be the clock crossing picking a different order; there's probably two concurrent processes where it is undefined which runs first. So far all simulators picked the same order we did, but here we might have a simulator doing it differently.

I would have to look further to see if this is it, though.