Chykon
Chykon
In the "References" section, the W3C version of the specification contains a reference to IEEE 754-2008 instead of IEEE 754-2019. Browser and PDF versions do not have this problem.
## Describe the bug A double `tick` is required to create a new timestamp. ## To Reproduce Use code: ```dart import 'package:rohd/rohd.dart'; class ExampleModule extends Module { ExampleModule(Logic inputA) {...
## Describe the bug Assignment missing from generated SystemVerilog. ## To Reproduce Use code: ```dart import 'dart:io'; import 'package:rohd/rohd.dart'; class ExampleModule extends Module { ExampleModule() { final out = addOutput('out');...
## Describe the bug The incoming signal behaves incorrectly in a certain case. Adding a useless assignment operator solves the problem. ## To Reproduce Steps to reproduce the behavior: 1....
## Describe the bug Time stamps are not created with a constant input signal, which is why the timing diagram does not represent the actual simulation process. ## To Reproduce...
### Motivation The presence of internal signals in the `WaveDumper` output can interfere with black box debugging (when only input/output ports is evaluated). ### Desired solution Add the ability to...
### Motivation When viewing `vcd` `StateMachine` is split into `sequential` and `combinational`, which introduces a bit of chaos due to the lack of context. It is better to let the...
## Description & Motivation This set of changes adds an easy way to locally check text formatting and link health in Markdown files. **TODO:** Add required dependencies to GitHub Codespaces...
### Motivation The comment style in the `example/tree.dart` example is different from the other examples. Subjectively, it is more difficult for beginners. ### Desired solution Rewrite the comments, linking them...
### Describe the bug The order in which `clock` is connected to module inputs affects how the circuit behaves. The first screenshot shows the correct behavior, the second shows the...