Time stamps are not created when the input signal is unchanged

[chykon]

Describe the bug

Time stamps are not created with a constant input signal, which is why the timing diagram does not represent the actual simulation process.

To Reproduce

Use code:

import 'package:rohd/rohd.dart';

class ExampleModule extends Module {
  ExampleModule(Logic inputA) {
    inputA = addInput('input_a', inputA);
    final out = addOutput('out');

    Combinational([
      out < inputA,
    ]);
  }

  Logic get out => output('out');
}

Future<void> main() async {
  Logic inputA = Logic();
  final exampleModule = ExampleModule(inputA);
  await exampleModule.build();
  WaveDumper(exampleModule);
  SimpleClockGenerator(2);
  inputA.inject(1);
  await Simulator.tick();
  await Simulator.tick();
  await Simulator.tick();
  await Simulator.tick();
  await Simulator.tick();
  /*
  inputA.inject(0);
  await Simulator.tick();
  await Simulator.tick();
  */
}

Open waves.vcd in viewer.

Expected behavior

The VCD file saved the signal history for each simulation step.

Actual behavior

The VCD file retained only step 0.

Additional details

Dart SDK version: 2.18.0 (stable) (Fri Aug 26 10:22:54 2022 +0000) on "linux_x64"

name: package

environment:
  sdk: '>=2.14.0 <3.0.0'

dependencies:
  rohd: ^0.3.2