Chykon

Yes, everything is correct now. Although constant inlining reduces the readability of SystemVerilog code. More readable would be: ```systemverilog module ExampleModule( output logic out ); logic val; assign val =...

And one more small remark already on the formatting of the generated code. Instead of `logic val;` it is now just an extra empty line: ```dart module ExampleModule( output logic...

Made a minimal example using one file. I also stumbled upon the sudden appearance of unknown bits. There are comments in the code regarding this. Maybe these problems are somehow...

Further shortening of the code: ```dart import 'dart:io'; import 'package:rohd/rohd.dart'; class ExampleModule extends Module { ExampleModule(Logic codepoint) { codepoint = addInput('codepoint', codepoint, width: 21); final bytes = addOutput('bytes', width: 32);...

I also seem to have missed the fact that the 24 most significant bits are unknown even though the `zeroExtend` operation is in progress.

Checked - everything works. Great job!

Perhaps it's better to use `subAssign` instead of `diffAssign`?

But then the use of `FlipFlop` will become not so convenient: you will have to use `input()`. Or am I not understanding something? **UPDATE:** Yes, I misunderstood this. The `clk`...

There is a problem with the `t_class_mod_bad` test: since the check for an invalid left operand of the scope resolution operator now happens earlier, the new error message overrides the...

I can't for now, but if someone wants to continue working on PR, I don't mind.