Chih-Min Chao

@nikita890-art Could you provide a branch pointing to your repo or patches ? It is hard to tell what goes wrong.

It is virtual address.

interesting, The vector amo instructions have been removed from source. Do you still need them ?

The performance counter number and behavior are implementation-defined. In current spike, counter number >= 3 are implemented as constant zero register (write allow read zero). You need to modify https://github.com/riscv-software-src/riscv-isa-sim/blob/4841ad0238f0b71ca86fb28974765495cc0c34a9/riscv/processor.cc#L261

@liweiwei90 You may be interested at that.

Separate the bf16 part into https://github.com/riscv-software-src/riscv-isa-sim/pull/1446

I agree to remove them and we could dig out the implementation from log in future.

@hanfeng0114 Could you send a PR for that ?

Could you try this #485 ?

It works and the opcode "00c5f50b" is illegal instruction because it hits https://github.com/riscv/riscv-isa-sim/blob/983abeaa9fb9c9c5cc8b318fdad11305a88021f3/customext/dummy_rocc.cc#L15. But the disassemble doesn't handle extension initialization from "--extension" path well. I will send another PR to...