riscv-isa-sim
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riscv-software-src
RISCV32 mhpmcounter3h-mhpmcounter31h counter CSRs not working
I am trying to cause an overflow in 32 bit architecture. Writing to the lower 32 bit csr register mhpmcounter3 works; however; whenever I write to the mhpmcounter3h register, the value stays at 0. Even when the mhpmcounter3 overflows, the value of mhpmcounter3h does not change either.
Are these CSRs not implemented currently in Spike? If not, where should I add its implementation.
The performance counter number and behavior are implementation-defined. In current spike, counter number >= 3 are implemented as constant zero register (write allow read zero). You need to modify https://github.com/riscv-software-src/riscv-isa-sim/blob/4841ad0238f0b71ca86fb28974765495cc0c34a9/riscv/processor.cc#L261
I am trying to cause an overflow in 32 bit architecture. Writing to the lower 32 bit csr register mhpmcounter3 works; however; whenever I write to the mhpmcounter3h register, the value stays at 0. Even when the mhpmcounter3 overflows, the value of mhpmcounter3h does not change either.
Are these CSRs not implemented currently in Spike? If not, where should I add its implementation.
Hey Youssef, Where can i know what mhpmevent values pair with what instructions for me to increment counter and to cause overflow based on sscofpmf extension
