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Note after discussion with @AngelaGonzalezMarino: I will change how I define types before spreading them. I have not embraced a specific style yet and I am not consistent. I’m sometimes...

Status of my version of the branch: smoke tests pass, ASIC synthesis passes too. However, I encounter Xilinx related issues, which I will have to fix.

Hello @spidugu444 Is it okay for you now ?

Hello, here is a similar issue: ```systemverilog module something (); always_comb begin //aaaaaaaaaaaaaa\ //aaaaaaaaaaaaaaaaaaaaaaaaa for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin $fatal(); end end endmodule ```...

This issue should be resolved with #1896 If so, can you close it, please @CoralieAllioux

Is it what you are looking for? https://github.com/openhwgroup/cva6/tree/master/util/gcc-toolchain-builder

For the VCD file, IIRC it should be in `verif/sim/out_$(date -I)/veri-testharness_sim/`

- CI simplification done, with a distinct workflow to run on master once a week - PR #1517 merged - do not run heavy tests if a smoke test fails....

- Fewer jobs are run thanks to https://github.com/openhwgroup/cva6/pull/1535 which changes PR pipelines to be *dev* instead of *regress*. However there is no job status checker in *dev* pipelines yet: added...

This description includes notion of code coverage, which is the topic of https://github.com/openhwgroup/cva6/issues/1436 However the current task focuses on "when is each job run?".