Generation of VCD for cva6 using verilator

[spidugu444]

Hi All,

I am trying to enable vcd on verilator for cva6 core, could anyone suggest where to enable vcd in core-v-verif environment.

Thanks in advance.

[MikeOpenHWGroup]

@JeanRochCoulon, @Gchauvon, @ASintzoff, can either of you answer @spidugu444's question?

[zchamski]

@MikeOpenHWGroup , @spidugu444 : this is currently work-in-progress at my side because the task is not exactly straightforward. First shareable results could arrive as soon as the end of this week (Sep 2).

[zchamski]

The current state of work is available as PR #1417 and its companion PR in CVA6 https://github.com/openhwgroup/cva6/pull/954.

The waveform support is operational on VCS and Verilator setups and is controlled by the same variables in each evnrionment (see the description of the PR at the top of this page.)

Please note that the usage of the DEBUG variable is subject to change (it is likely to become invisible to the user.)

[zchamski]

Unified tracing support is now available in the mainline for both Verilator and VCS. The revised PRs #1427 and https://github.com/openhwgroup/cva6/pull/965 have been merged into their respective base branches:

• core-v-verif: branch cva6/dev, commit https://github.com/openhwgroup/core-v-verif/commit/8f9e8e03b50ee846e80de837f3bca21432715e84
• cva6: branch master, commit https://github.com/openhwgroup/cva6/commit/871be7c7943820ebe72c85c72f9af1164a50dc32.

[MikeOpenHWGroup]

Hi @spidugu444, does #1427 satisfy your request? If so, please close this issue. Thanks.

[cathales]

Hello @spidugu444

Is it okay for you now ?

[MikeOpenHWGroup]

Closing because the issue is deemed to be resolved and the originator (@spidugu444) has not responded in four months.