Carlos Eduardo

Kernel errors on running in ARM64

1

I'm running a Prometheus-operator deployment that uses configmap-reload image on a Rock64 ARM64 board. I see in the logs the following error in journalctl: ``` Mar 13 10:15:27 kubenode2 kernel:...

[Feature] Ignore certain libraries/plugins

2

It would be great to define a list of libraries or plugins to be ignored. For example, on VSCode with Metals, it creates a `project/metals.sbt` file with `sbt-bloop` as a...

Configuring no trigger for some commands on Zsh returns error

7

- [x] I have read through the manual page (`man fzf`) - [x] I have the latest version of fzf - [x] I have searched through the existing issues ##...

FPGA code generation improvents

1

The core generation for FPGA fails due to: - [x] Memory initialization is generated only inside the ifndef SYNTHESIS block #4752 - -> Fixed by https://github.com/llvm/circt/issues/4752#issuecomment-1696021770 - [x] Synthesizing generated...

Create scala-extensions module for Scala 3

1

This PR adds a scala-extensions module for a Scala 3 DSL similar to the existing Kotlin DSL. This extension is important since rest-assured is heavily used in Quarkus tests for...

Add `$schema: ` syntax to load JSON schema for YAML files

2

### Is your enhancement related to a problem? Please describe. Recently, Intellij added a syntax to load a JSON schema for YAML files in the format of `$schema: https://schemaURL`. It...

Chisel design with inline blackbox verilog generates `.sv` output with filenames at the end

4

On my Chisel design, I have some modules that use inline blackbox Verilog code (Eg. https://github.com/carlosedp/chiselv/blob/dd33dc558fb703adc95fd2c719367e5f2dc0e709/chiselv/src/GPIO.scala#L49) When going thru firtool, the generated `.sv` file have the "blackboxed" verilog code inlined...

[FIRRTL] Feature Request: Provide a similar `--target:fpga` behavior for FPGA-suited targets

2

On FIRRTL, there is a command-line flag (currently `--target:fpga`) that applies some transformations better suited to FPGA targets. Details are in https://github.com/chipsalliance/firrtl/blob/master/src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala 1) Enable the [[firrtl.passes.memlib.InferReadWrite]] transform to reduce port...

Add Scala executable via GraalVM. Bump versions.

1

Add Scala executable via GraalVM Native-image. Bump Scala and ScalaNative versions. @lolgab would you 👀?

As many DAPs and players don't support using the "Album Artist" tag, they mess up albums that contains collaboration from artists (the Artist don't match the Album Artist) and the...