Carlos Eduardo
Carlos Eduardo
Is there a reason to have the object extending `App` on most module files like below? ```scala import chisel3.stage.ChiselStage ... ... object LoadStoreObj extends App { (new ChiselStage).emitVerilog(new LoadStoreWrapper(64, 128*1024,...
I got a suggestion that one option to address the memory limitation for running Micropython on FPGAs is instantiating the ECP5 DP16KD directly similar to: https://github.com/skristiansson/wb_sdram_ctrl/blob/master/rtl/verilog/dpram_ecp5.v I understand that this...
This PR adds support to Project XRay supporting Xilinx series 7 FPGAs. Currently I'm testing with Kintex 7 and a QMTech board. The work is based on https://github.com/kintex-chatter/xc7k325t-blinky-nextpnr and is...
This allow adding TCL scripts on pre-synthesize, pre-pnr and pre-bistream generation for the Libero backend. In the .core file, this would be defined like: ```yaml polarfireeval: files: - rtl/corescore_polarfire_eval_clock_gen.v: {...
Possible to simulate blinky on Verilator as a validation?
The latest script version show the POWER9 CPUs are shown as vulnerable to CVE-2018-3615 and CVE-2018-3640 but according to the docs below, these don't affect POWER9 processors, only Intel CPUs....
Is it possible to set the tab title based on the note title?
## Expected Behaviour Stopping faasd and faasd-provider should stop all containers. When the processes `faasd` and `faasd-provider` are stopped (with sysctl), it's expected that all containers should be stopped. ##...
## Expected Behaviour Currently faasd depends on a custom library based on weave net and has netlink/netns dependencies. The idea is to provide a built-in solution to fetch container IP...
On a Mikrotik router, if the note field mtxrNote (usually used for MOTD and etc) has more than 249 characters, the exporter times-out ### Host operating system: output of `uname...