FPGA code generation improvents

[carlosedp]

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The core generation for FPGA fails due to:

• [x] Memory initialization is generated only inside the ifndef SYNTHESIS block #4752 - https://github.com/llvm/circt/issues/4752 -> Fixed by https://github.com/llvm/circt/issues/4752#issuecomment-1696021770
• [x] Synthesizing generated files with Yosys threw a unexpected TOK_AUTOMATIC error #4751 - https://github.com/llvm/circt/issues/4751

The ideal scenario would be fixing:

• [ ] Chisel design with inline blackbox verilog generates .sv output with filenames at the end #4249 - https://github.com/llvm/circt/issues/4249
• [ ] Feature Request: Provide a similar --target:fpga behavior for FPGA-suited targets #4230 - https://github.com/llvm/circt/issues/4230

That would lead to having a single SV file without the need to split files and a flag to enable memory initialization for synthesis cleaning-up the chiselv.core file (Have a single Toplevel.sv and removing the --split-verilog params).

[carlosedp]

After the hack into firtool to correctly initialize the memory outside the ifndef, the reset in the core does not behave as expected. Need to investigate further.