Carlos Eduardo
Carlos Eduardo
Running as: `synth.f4pga.sh -v myfile.v -x constr.xdc -t Toplevel -d xc35 -p 384 -e DEFINE_1_=1 DEFINE_2_=2` Generates: `yosys -p ; tcl /Users/cdepaula/repos/f4pga/f4pga/wrappers/tcl/xc7.f4pga.tcl -l Toplevel_synth.log -DDEFINE_1_=1 -DDEFINE_2_=2 myfile.v`
I have a project where I need to pass a synthesis define due to an `ifdef` in the code. Using Trellis it works fine but using the `symbiflow_synth`, `symbiflow_pack`, etc...
### Is your feature request related to a problem? Please describe. Currently Metals can add the type annotation to methods, variables, etc but in case you need to change the...
In my core, I use Symbiflow tool to synthesize and generate bitstream to an Artix 7 FPGA. I recently needed to pass a vlogdefine to Yosys due to memory initialization...
I'm trying to use the f4pga flow for a Xilinx board but I'm getting the following error: ``` Traceback (most recent call last): File "/Users/cdepaula/python_bins/bin/fusesoc", line 8, in sys.exit(main()) ^^^^^^...
Since Chisel/Firtool now requires a synthesis define `ENABLE_INITIAL_MEM_=True` to be able to initialize memories with external files (readmemh/readmems), this define has been added to the chiselv.core file but was not...
This PR adds a Scala 3 example and also reverts the build of the scala-extension module to the Scala LTS version (3.3.3) instead of the 3.4 series.
### Current behavior I had a script which used Scala Index API to check for Mill/Ammonite plugin versions and show updates. I used something like `https://index.scala-lang.org/api/artifacts/com.goyeau/mill-scalafix_mill0.11_2.13` in the API but...