mtkcpu
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bieganski
RISC-V CPU implementation in Amaranth HDL (aka nMigen)
currently for Debug Module registers fields, like `cmderr` field of `abstractcs`, that due to Debug Specs is `W1C` (write 1 clears the corresponding bit) we need to explicitely write corresponding...
Currently porting third-party peripherals to `mtkCPU` may be problematic, because what is called `Wishbone` in the CPU code (we have `WishboneBusRecord`, `GenericInterfaceToWishboneMasterBridge` and `WishboneSlave` classes) does _not_ implement a real...
# What happens? Currently address decoder allows for whole 32-bit space to be used, which is a killer for FPGA resources. Relevant code: ```py with m.If((req_addr >= start_addr) & (req_addr
# What happens? For non-leaf PTE (page table entries) Risc-V spec says that neither A, D or U bits can be set. Page-fault exception should be thrown when found such...
# What happens? Virtual memory system in `mtkCPU` is well-tested, but only for proper memory configuration. For error conditions only error register is written (no trap occurs at all): ```py...
for example: ``` auipc x2, 1 # 0x80001000, naturally aligned lw x1, 1(x2) # load 4 bytes from 0x80001001 ``` will not raise and will return wrong result. when issue...
# Description ``` mateusz@test:~/tb/github/mtkcpu$ riscv-none-elf-gdb -x board/breakpoint_example.gdb sw/uart_tx/build/uart_tx.elf GNU gdb (xPack GNU RISC-V Embedded GCC x86_64) 13.2 Copyright (C) 2023 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3...