riscv-dv mmu tests not fully valid

[bieganski]

What happens?

For non-leaf PTE (page table entries) Risc-V spec says that neither A, D or U bits can be set. Page-fault exception should be thrown when found such non-leaf page during page-walk.

However, riscv-dv generates non-leaf pages with those bits set, expecting hardware to proceed without error. Spike simulator however traps (described in the issue below). To obtain Spike simulation log without traps, I commented out corresponging lines inside riscv-isa-sim code (descrobed in the issue below).

Once MMU traps are supported in mtkCPU (https://github.com/bieganski/mtkcpu/issues/8), Spike's behavior should be reproduced.

related issue in riscv-dv repository: https://github.com/google/riscv-dv/issues/846