interconnect to be unified

[bieganski]

Currently porting third-party peripherals to mtkCPU may be problematic, because what is called Wishbone in the CPU code (we have WishboneBusRecord, GenericInterfaceToWishboneMasterBridge and WishboneSlave classes) does not implement a real Wishbone interface - indeed, it's similar, but much simplified.

Some examples of discrepancies:

• no strobe signal is used at all - there is an assumption, that strobe == cyc
• no tags are present
• no select signal - chip select logic is moved to address decoder, that switches peripherals based on request address as shown here

However, ideally we should implement and functionally verify Wishbone Bus, to make it easier for users to port their own peripherals.

[robtaylor]

Do check out the new Interfaces RFC in Amaranth. We now discuss RFCs every Monday at 1700 UTC on the irc channel.

[bieganski]

oh, good to know, thank you! for sure will check it out.