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RISC-V CPU implementation in Amaranth HDL (aka nMigen)

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AmaranthHDL: bump to 0.5.

bieganski avatar bieganski

synthesis timing improvements

bieganski avatar bieganski

sw: add 'uart_tx_timer_irq' example (with UART).

bieganski avatar bieganski

Amaranth-boards version not specified causing py requirements installation to fail.

Hello - This is a really nice project, the debug module and able to debug is really nice. I cloned this repo today and started to follow the quickstart but...

timoksn avatar timoksn

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RISC-V CPU implementation in Amaranth HDL (aka nMigen)

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