Mateusz

is it possible for `demo_darknet2onnx.py` script to add support for Yolo-Fastest (https://github.com/dog-qiuqiu/Yolo-Fastest/) configs? ```bash python3 demo_darknet2onnx.py yolo-fastest.cfg 80classes.txt yolo-fastest.weights image.jpg 0 ``` produces errors: ``` unknown type dropout unknown type...

unexpected behavior on direct_io = True

2

I slightly modified `example/hello.py`, so that it uses `direct_io`, and I cannot explain the result. With `./test` mountpoint, the command `cat ./test/hello` works fine with `direct_io = False`, but enters...

build instructions for Ubuntu 22.04

16

i did some tweaks to make all the software compile and (at least) GUI works with newest Ubuntu. Not tested further due to lack of hardware. ```sh git clone https://github.com/bieganski/linuxtrack...

python interface to libbpf

10

newcomer question here. eBPF tool basically consists of userspace controller program (compiled for native CPU architecture) that makes calls to libbpf, and a loadable program compiled for `bpf` architecture, let's...

[CO-RE] relocations are not emitted for tracepoint 'context' argument.

5

```c SEC("tracepoint/syscalls/sys_exit_openat") int tracepoint__syscalls__sys_exit_openat(struct syscall_trace_exit* ctx) { bpf_trace_printk("AAAA %d", ctx->ret); return 0; } ``` And corresponding `llvm-objdump -rd` output: ``` Disassembly of section tracepoint/syscalls/sys_exit_openat: 0000000000000000 : 0: 79 12 10...

TODO

currently for Debug Module registers fields, like `cmderr` field of `abstractcs`, that due to Debug Specs is `W1C` (write 1 clears the corresponding bit) we need to explicitely write corresponding...

interconnect to be unified

2

Currently porting third-party peripherals to `mtkCPU` may be problematic, because what is called `Wishbone` in the CPU code (we have `WishboneBusRecord`, `GenericInterfaceToWishboneMasterBridge` and `WishboneSlave` classes) does _not_ implement a real...

# What happens? Currently address decoder allows for whole 32-bit space to be used, which is a killer for FPGA resources. Relevant code: ```py with m.If((req_addr >= start_addr) & (req_addr

# What happens? For non-leaf PTE (page table entries) Risc-V spec says that neither A, D or U bits can be set. Page-fault exception should be thrown when found such...