Anup Patel
Anup Patel
Well, "H" is not a separate privilege mode in itself like "M", "S" and "V" modes because it adds additional capability to S-mode so that we can virtualize "S" and...
If you have mix of cache-coherent and non-cache-coherent devices on your platform then you also need Svpbmt and Zicbom ISA extensions.
I suggest sharing a draft proposal for SBI OP-TEE extension on the OpenSBI and PRS TG mailing list will be a good starting point. Regards, Anup
@liushiwei007 please send plain text message on OpenSBI mailing list
Prefer fw_dynamic.bin if the booting stage before OpenSBI can load FDT at the appropriate location and tell it's location to OpenSBI. In fact, QEMU and U-Boot use only fw_dynamic.bin as...
Once spec is frozen, we will ask RISC-V international to host it on RISC-V website Regards, Anup
@gfavor I accidentally assigned you this issue. Actually I wanted to bring to your notice some other discussion at https://github.com/riscv/riscv-aclint/commit/8c08bc744e80fbf16f0faa4d2312059d7725b8bc
For raw images passed as payload, we don't have option except use some heuristic value as gap between payload_end and DTB. For ELF images, we can parse size of BSS+SBSS...
Spike does not clear the VS-interrupt bits tied to 1 in mideleg when misa.H bit is updated. We have to fix Spike for this. Regards, Anup
I have send PR to Spike repo. Link https://github.com/riscv/riscv-isa-sim/pull/537/