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Smp Linux hardware support for dual core

Open ErShubhamYY opened this issue 2 years ago • 2 comments

We have designed single core and planning to extend it to dual core and boot smp Linux(both core are identical). We have found out that we need following things to be implemented correctly.

  1. Cache coherence
  2. Atomic instruction to be implemented for dual core
  3. Inter processor interrupts(use aclint for that)
  4. Memory barrier synchronisation instruction (fence, fence.i) Apart from that do anything else need to be considered to make dual core smp Linux compatible. We are building smp Linux using buildroot tools.

ErShubhamYY avatar Apr 06 '23 09:04 ErShubhamYY

If you have mix of cache-coherent and non-cache-coherent devices on your platform then you also need Svpbmt and Zicbom ISA extensions.

avpatel avatar Apr 06 '23 10:04 avpatel

If you have mix of cache-coherent and non-cache-coherent devices on your platform then you also need Svpbmt and Zicbom ISA extensions.

Do we have to implement svpbmt and zicbom even if we hardcode pbmte , cbie and cbcfe bit to 0 in menvcfg csr register?

ErShubhamYY avatar Apr 07 '23 22:04 ErShubhamYY