arthurjolo

Results 32 comments of arthurjolo

segfault in resizer repair_timing -setup

I tried multiple times to reproduce the crash but wasn't able to. I am going to check TSAN and ASAN for any thread issues.

Re-tighten hold violations count for ngt45/bp_fe_top

PR [#6846](https://github.com/The-OpenROAD-Project/OpenROAD/pull/6846) was merged, but the metrics had already been re-tighten.

CTS / resizer hits max buffer count limit in hold violations with nangate45 bp_quad

I checked the clock tree and it looks like it is fine. On `bp_clk` there is a small issue with the macro tree, but the worst paths do not go...

CTS / resizer hits max buffer count limit in hold violations with nangate45 bp_quad

For `sdi_a_clk` the avg arrival time is ≃ 0.26 ns, while for `router_clk` is ≃ 1.28 ns. This created the big hold slacks. However, I believe the main problem is...

CTS / resizer hits max buffer count limit in hold violations with nangate45 bp_quad

I see no synchronization, what I mentioned that I believed it was another register on the path was just a clk_buff that I got confused. The worse paths are just...

CTS / resizer hits max buffer count limit in hold violations with nangate45 bp_quad

@rovinski `To` is connected directly to another register. So This seems to a be a synchronizers, they even have "sync" on their name 😄 However on the other cases where...

Cts enable obstruction aware

Secure-CI is has few metrics failures and a PR has been created to update them, a7/mock_array and ng45/bp_fe have degradation on timing metrics due to a bad placement decision from...

CTS-Avoid level balance buffers overlap.

Secure Ci is passing, only need to update a antenna diode count metric for 1 design. I am going to create a PR for this update.

CTS-Avoid level balance buffers overlap.

Close as balance levels is now obsolete.

Clock tree appears to be unbalanced for BoomTile running at 833 MHz

@jeffng-or Do you know if there are any clock gaters on this design? Clock gaters have some issues currently.