arthurjolo

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Clock tree appears to be unbalanced for BoomTile running at 833 MHz

I am going to open the design and take a close look on it, but I don't think this is due to the splitting of macros from std cells. On...

Clock tree appears to be unbalanced for BoomTile running at 833 MHz

One thing that I noticed from Jeff's dump is that on the `array_1_0_ext/R0_clk` path there are 7 wire buffers between the leaf clk buffer and the CK pin, while on...