Ajay Nath

Olof, ``--depth=1`` will certainly work. What about a specific branch name?

Hi Stefan and Olof, Thanks for PR and the comments/justifications. Agreed that an itemized waiver list is better than blanket disabling of linter checks. We'll discuss ramifications and respond. Thank...

Hi @kidonglee, We are meeting ~600Mhz for 16nm technology, **worst case corner**. Your scale factor seems very large! Based on that, your target frequency > 700Mhz. With the slack you...

Do note that one of the reasons we do not provide synthesis scripts is that there are several key factors, such as technology node, library vendor, memory vendor/type, synthesis methodology,...

Hi @SyoAnd, It is full verification, per the spec. However, this verification environment is not currently part of this opensource effort. So you would need to first plan, build and...

Hi @mablinov, are you explicitly building yor SweRVolf with ICCM enabled? The default build (see configs/swerv.config) is to build with ICCM disabled (i.e not present). The breadcrumb to look for...

It can be set to 0 via `-set=fpga_optimize=0`

From the designer: **Part 1**: “_I see that when num_valids[3:0] ≤ 4'h2, you just shift the GHR left without retaining the MSBs_” This is only true for small BHTs that...

This is the PC address that the core is going to fetch after flushing the entire pipeline due to one or more of: - Interrupt taken, - mispredict from i0...

Hi @kingstone1927 , Follow these signals from the dec/tlu block: ``` design/dec/dec.sv: output logic dec_tlu_flush_noredir_wb , // Tell fetch to idle on this flush design/dec/dec.sv: output logic dec_tlu_flush_leak_one_wb, // single...