Cores-VeeR-EL2
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chipsalliance
Synthesis clock speed is very slow
Hi,
I synthesized SweRV-EL2 and Rocket Chip with default configuration Rocket Chip can be synthesized up to 500MHz without timing slack. However, SweRV-EL2 can be synthesized up to 300MHz without timing slack, in the same condition. SweRV-EL2 is very slower than Rocket Chip. Is it reasonable results? Could you please give me a comment on the result.
Thanks.
Can you please share some details: a) Constraints you have used. b) Which synthesizer/version have you used ? c) Which tech node/lib have you used ?
Dear Codasip,
The synthesis condition is as follow,
- dc ver = 2016.03
- scale factor = 0.563 // margin
- clk = 400MHz // actual clock period = (1000/400)*0.563 = 1.41 ns
- jtag_clk = 10MHz // actual clock period = (1000/10)*0.563 = 56.3 ns
- clock transition value = 0.1
With above condition, the max timing slack is -0.24ns. FYI, I post the longest delay path, as below. Please check it.
Thanks
Startpoint: swerv/ifu/aln/rdpff/dout_reg[1]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: mem/iccm.iccm/red_lru/genblock.dffs/dout_reg[0]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
swerv/ifu/aln/rdpff/dout_reg[1]/CK 0.00 # 0.00 r
swerv/ifu/aln/rdpff/dout_reg[1]/Q ... ...
swerv/ifu/aln/U100/Y ... ...
swerv/ifu/aln/U822/Y ... ...
swerv/ifu/aln/U55/Y ... ...
swerv/ifu/aln/U104/Y ... ...
swerv/ifu/aln/U760/Y ... ...
swerv/ifu/aln/U82/Y ... ...
swerv/ifu/aln/U230/Y ... ...
swerv/ifu/aln/U171/Y ... ...
swerv/ifu/aln/U32/Y ... ...
swerv/ifu/aln/U31/Y ... ...
swerv/ifu/aln/U223/Y ... ...
swerv/ifu/aln/U17/Y ... ...
swerv/ifu/aln/U211/Y ... ...
swerv/ifu/aln/U291/Y ... ...
swerv/ifu/aln/U680/Y ... ...
swerv/dec/instbuff/U59/Y ... ...
swerv/dec/decode/U1519/Y ... ...
swerv/dec/decode/U873/Y ... ...
swerv/dec/decode/U1023/Y ... ...
swerv/dec/decode/U1008/Y ... ...
swerv/dec/decode/U181/Y ... ...
swerv/dec/decode/U397/Y ... ...
swerv/dec/decode/U182/Y ... ...
swerv/dec/decode/U408/Y ... ...
swerv/dec/decode/U71/Y ... ...
swerv/dec/decode/U248/Y ... ...
swerv/dec/decode/U221/Y ... ...
swerv/dec/decode/U433/Y ... ...
swerv/dec/decode/U419/Y ... ...
swerv/exu/U448/Y ... ...
swerv/exu/U222/Y ... ...
swerv/exu/i_alu/U858/Y ... ...
swerv/exu/i_alu/U54/Y ... ...
swerv/exu/i_alu/U208/CON ... ...
swerv/exu/i_alu/U783/Y ... ...
swerv/exu/i_alu/U320/Y ... ...
swerv/exu/i_alu/U847/Y ... ...
swerv/exu/i_alu/U794/Y ... ...
swerv/exu/i_alu/U793/Y ... ...
swerv/exu/i_alu/U127/Y ... ...
swerv/exu/i_alu/U78/Y ... ...
swerv/exu/i_alu/U618/Y ... ...
swerv/exu/i_alu/U886/Y ... ...
swerv/ifu/mem_ctl/U700/Y ... ...
mem/icache.icm/ic_tag_inst/U22/Y ... ...
mem/icache.icm/ic_tag_inst/U21/Y ... ...
swerv/ifu/mem_ctl/U730/Y ... ...
swerv/ifu/mem_ctl/U670/Y ... ...
swerv/ifu/mem_ctl/U671/Y ... ...
swerv/ifu/mem_ctl/U674/Y ... ...
swerv/ifu/mem_ctl/U673/Y ... ...
swerv/ifu/mem_ctl/U85/Y ... ...
swerv/ifu/mem_ctl/U87/Y ... ...
swerv/ifu/mem_ctl/U79/Y ... ...
mem/icache.icm/ic_data_inst/U64/Y ... ...
mem/icache.icm/ic_data_inst/U53/Y ... ...
swerv/ifu/mem_ctl/U667/Y ... ...
swerv/ifu/ifc/U261/Y ... ...
swerv/ifu/ifc/U259/Y ... ...
swerv/ifu/mem_ctl/U90/Y ... ...
swerv/ifu/mem_ctl/U89/Y ... ...
swerv/dma_ctrl/U10/Y ... ...
swerv/dma_ctrl/U660/Y ... ...
swerv/ifu/mem_ctl/U88/Y ... ...
swerv/ifu/mem_ctl/U64/Y ... ...
swerv/ifu/mem_ctl/U70/Y ... ...
swerv/ifu/mem_ctl/U128/Y ... ...
swerv/ifu/mem_ctl/U2031/Y ... ...
mem/iccm.iccm/U215/Y ... ...
mem/iccm.iccm/U200/Y ... ...
mem/iccm.iccm/U726/Y ... ...
mem/iccm.iccm/U727/Y ... ...
mem/iccm.iccm/U83/Y ... ...
mem/iccm.iccm/U564/Y ... ...
mem/iccm.iccm/U302/Y ... ...
mem/iccm.iccm/U662/Y ... ...
mem/iccm.iccm/red_lru/U3/Y ... ...
mem/iccm.iccm/red_lru/genblock.dffs/dout_reg[0]/D 0.00 1.66 r
data arrival time 1.66
clock clk (rise edge) 1.41 1.41
clock network delay (ideal) 0.00 1.41
mem/iccm.iccm/red_lru/genblock.dffs/dout_reg[0]/CK 0.00 1.41 r
library setup time 0.01 1.42
data required time 1.42
--------------------------------------------------------------------------
data required time 1.42
data arrival time -1.66
--------------------------------------------------------------------------
slack (VIOLATED) -0.24
Dear Codasip,
Did you check my comment above ? Actually, I wonder if the difference in speed between rocket and SweRV-EL2 is reasonable or not. If you have compared the speed of them, could you please let me know the results ? I am sorry to bother you but please help.
Thanks
Hi @kidonglee, We are meeting ~600Mhz for 16nm technology, worst case corner.
Your scale factor seems very large! Based on that, your target frequency > 700Mhz. With the slack you show, the result is closer to 600. Why do you need such a large scale factor, BTW?
Do note that one of the reasons we do not provide synthesis scripts is that there are several key factors, such as technology node, library vendor, memory vendor/type, synthesis methodology, margins, clk skew, configuration, that will have a sizable impact on synthesis results.
Hi @kidonglee, We are meeting ~600Mhz for 16nm technology, worst case corner.
Your scale factor seems very large! Based on that, your target frequency > 700Mhz. With the slack you show, the result is closer to 600. Why do you need such a large scale factor, BTW?
Dear aprnath,
I understand what you mean. However, what I want to know is the difference between ocket and SweRV-EL2. I just wonder if the difference of clock speed between them is reasonable or not. If you also compared them, please let me know the results.
Than you very much for the kindness.