Core Design validation/verification

[SyoAnd]

Hello I see in the documentation that this core has been validated to compliance with RISC-V spec. But it is not stated to what level the core is checked. Is it a simple compliance check, validation, or a full verification?

I want to make an addition to the core, but in doing so, I want to make sure that I don't break the execution of the core in any way. How would I do this the best way? I have looked at several tools for validation, RISCOF being the latest one. Will I be able to use it for validation of this design?

[aprnath]

Hi @SyoAnd,

It is full verification, per the spec.

However, this verification environment is not currently part of this opensource effort. So you would need to first plan, build and execute a full verification suite, in case you wish to make changes/additions :-( . Or you could possibly use some incremental equivalency checking mechanisms to incrementally check your localized changes.