Alessandro Comodi

Results 71 issues of Alessandro Comodi

Signed-off-by: Alessandro Comodi

type-utils

This PR is based on top of #2137 and #2139 it requires a rebase once they are merged. This PR adds the new qlf k6n10 device

lang-verilog
lang-xml
lang-makefile
lang-python
type-infra
type-utils

Signed-off-by: Alessandro Comodi This PR adds the possibility to instruct yosys on which kind of frontend to use to parse input files. https://github.com/SymbiFlow/symbiflow-examples/issues/113 shows that there are some riscv CPU...

This PR supersedes https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1251. It is rebased on top of the current master. Routing seems to take a reasonable amount of time (~8 minutes) w.r.t. the previous tests which took...

lang-verilog
type-docs
lang-python

Signed-off-by: Alessandro Comodi This PR enables latches by modifying the techmap sim and map files. I have added a basic latch test, with LDPE and LDCE instantiations, and tested them...

lang-verilog
lang-xml
type-utils
type-vpr

This is an initial implementation of the URay Slicel pb_type, with all its basic primitives. Primitives status: - [x] LUT - [x] F[789]MUXes - [x] FFMUXes - [x] OUTMUXes -...

lang-xml
type-utils
third-party
type-vpr
arch-artix7

Signed-off-by: Alessandro Comodi

type-docs

Signed-off-by: Alessandro Comodi This PR adds the possibility to split an edge during edge creation by adding an additional node that corresponds to custom segments. This is to address the...

lang-python
type-utils

This issue is to keep track of the issue reported here: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1776. This issue has been split from https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1788, as it tackles a different problem. ## Problem statement The auto-generated...

Each `GTP_COMMON` in the Series7 has two different `IBUFDS_GTE` from which it can get the differential clock signals. The `GTP_COMMON` itself has two `GTREFCLK` inputs, each of them exclusively connected...