Alessandro Comodi

FPGA interchange: add RR graph generation

5

#### Description This PR adds the RR graph generation, built from the RR interchange data. The code present in the PR does mainly the following things: - reworks and reorganizes...

#### Proposed Behaviour Currently, with the new GH action custom runner we have more flexibility in the number of machines that we can spawn per CI check. Therefore we can...

#### Proposed Behaviour With the GH actions transition we need to store the artifacts on GCP or otherwise they'll have an expiration date and can get removed from GH ####...

Separate VTR nightly build for each set of benchmarks

2

#### Proposed Behaviour The Nightly Kokoro CI is currently running two sets of test: - ISPD benchmarks - Titan benchmarks With https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1564 there will also be the Symbiflow benchmarks enabled....

As far as I understand, VPR is not able to define a constant generator leaf pb type, unless it is a LUT. In real devices, there are logic block are...

#### Description This PR is a follow-up to https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1893, and is based on top of it. This PR adds the FPGA interchange netlist reading capability, as well as a very...

This fixes a situation for which the `ADI1MUX` in `SLICEMs`, when in `DRAM64` mode, could have an input directly connected to the `BI` `SLICEM` input port, therefore bypassing the `BDI1MUX`...

Signed-off-by: Alessandro Comodi

Signed-off-by: Alessandro Comodi

gtp: add full LiteSATA example with workarounds

3

Signed-off-by: Alessandro Comodi This generates a bitstream that can read/write on an M.2 SSD through SATA, using the following [sata adapter](https://github.com/antmicro/fmc-sata-adapter) and a `nexys_video` board