f4pga-arch-defs
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Fix IBUFDS_GTE to GTP_COMMON connection
Each GTP_COMMON
in the Series7 has two different IBUFDS_GTE
from which it can get the differential clock signals. The GTP_COMMON
itself has two GTREFCLK
inputs, each of them exclusively connected to one of the IBUFDS_GTE
.
Using Vivado, having the connection from an IBUFDS_GTE to a "physically unconnected" GTREFCLK
input is still allowed as the tool apparently rearranges the netlist. This isn't the case in Yosys+VTR, where, the connection will not be present.
This issue is still open. Has this connection problem not been fixed yet?