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Published 20 hours ago • verified publisher icon verilog-to-routing

VPR: interchange: add initial support for the interchange netlist frontend

Open acomodi opened this issue 2 years ago • 0 comments

Description

This PR is a follow-up to https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1893, and is based on top of it.

This PR adds the FPGA interchange netlist reading capability, as well as a very basic unit test that, for the time being is checking whether the netlist can be read without errors.

Motivation and Context

Alongside with the architecture reading, the netlist can also be expressed by means of the Interchange format.

How Has This Been Tested?

Basic unit test added to read in a test interchange netlist file.

Types of changes

  • [ ] Bug fix (change which fixes an issue)
  • [x] New feature (change which adds functionality)
  • [ ] Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • [ ] My change requires a change to the documentation
  • [ ] I have updated the documentation accordingly
  • [x] I have added tests to cover my changes
  • [x] All new and existing tests passed

acomodi avatar Oct 25 '21 15:10 acomodi