Andrew Brown
Andrew Brown
I think it should be possible to determine that the shifts are by constant value so the extra shift + immediate instructions may not be necessary. I think the code...
I've been saying in the other inefficiency issues that we should document these before closing. @dtig brought up that someone from Intel was going to look into creating such a...
> This is very specifically an Intel ISA quirk because `pshufd/pshufw/pshufb` all have different semantics I don't think the key is actually the different semantics, it's that these instructions can't...
Can I get permissions to re-open this? I think the actionable part is to document the possible lowerings that improve the situation in the "implementor's guide" document (do we have...
Can we add WAMR, Wasmtime, and Lucet to that list? Perhaps WAVM and SSVM as well?
(Should we update the implementation status document for those runtimes as well?)
I guess I assumed that when the backing memory for a Wasm `memory` operation is allocated, it would be allocated at a 16-byte aligned boundary so that any Wasm aligned...
> the engine would be responsible for handling that fault and performing the v128.store via some other slow path @tlively, can you point me to how this is done in...
So LLVM can only ever emit a `MOVUPS` when it sees a `v128.store`? It can't use the alignment hint to generate a `MOVAPS`?
See https://github.com/bytecodealliance/sightglass/pull/104 for alternatives to this (e.g. multi-stage builds).