PoC
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VLSI-EDA
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
At [Enclustra](www.enclustra.com), we have been considering open-sourcing our clock-crossing VHDL blocks and constraints files. However, I attended a presentation by @Paebbels at FPGA Conference Europe in Munich and I saw...
Hello, I tried to setup PoC as described in the Quickstart Guide in the readme. After experiencing the bug described in #62 and applying the suggested fix (renaming PoC.py in...
Dear, do you know how to define the use of 512 word 16bit RAM (preloaded during FPGA power on and acting as ROM) in vhdl (using GHDL & Yosys) for...
Add synthesizer support for Synopsys Synplify Pro. **Note:** Synplify is also included in Lattice Diamond and can be used as an alternative to the Lattice Synthesis Engine.
PoC currently provides only an [adapter](https://github.com/VLSI-EDA/PoC/blob/release/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl) which maps between the PoC.Mem interface and the native interface of the Xilinx MIG IP core. This adapter must be instantiated together with the...
hi everyone. i faced with pyIPCMI problem. somebody can help me? how can i solve this problem? i referenced POC library document 1.2.0. and exactly followed chap 5.1 to 5.4.1....
Some Submodule paths, named pyIPCMI and uvvm failed when cloning recursive.
The unit "misc_strobegenerator.vhdl" is needed by io_7SegmentMux_BCD.vhdl module, but it is missing on github. Is it available elsewhere? Could someone check it in?
In the README.md of the fifo folder a FIFO for dependent clocks is mentioned but the corresponding file `fifo_dc_got.vhdl` is missing.
Hi, when configuring PoC for Intel Modelsim Starter Edition, I encountered the following problem: ``` Configuring installed tools --------------------------- Configuring PoC Installation directory: /home/johannes/tries/foss-applications/PoC (found in environment variable) Configuring Git...
