Implement wrapper for DDR3 memory controller on Xilinx KC705 board

[mzabeltud]

PoC currently provides only an adapter which maps between the PoC.Mem interface and the native interface of the Xilinx MIG IP core. This adapter must be instantiated together with the netlist generated by the Xilinx IP core generator. PoC already supports netlist generation using Xilinx ISE (IP core PoC.xil.mig.KC705_MT8JTF12864HZ_1G6). An XCI file for Xilinx Vivado can be found in PoC-Examples.

Requested features:

1. The temperature monitor should be excluded by default, when the MIG IP core is generated using Xilinx ISE. The device temperature should be provided by another PoC IP core, see #30.

2. Provide a XCI file for Xilinx Vivado. Netlist generation should allow a configurable user clock frequency, because the clock for the native interface is provided by the MIG IP core itself. The temperature monitor should be excluded, as above.

3. Implement a wrapper instantiating the adapter and the netlist:

   • Suggested name: "ddr3_ctrl_KC705" or "ddr3_wrapper_KC705".

   • User side interface: PoC.Mem interface and device temperature.

   • DDR3 side interface: as required by the MIG IP core. Note: the top-level DDR3 port names must match that of the MIG IP core because the MIG generates constraints also for the top-level ports (IO standard, slew rate, ...). The constraints could not be adapted because Vivado embeds them in the generated design checkpoint.

   • Configuration parameter: DIMM : string selecting the proper IP core configuration (DIMM timing) from PoC.xil.mig. Alternatively, the timing should be configurable during netlist generation.

   • For Vivado, the netlist must be instantiated using a component declaration.

Related: update memory test and cache test examples in PoC-Examples.

[KedharGuhan]

Hey, is this issue open to take up? Can someone brief me with some deets I'd like to contribute.