Tony Reinberger

Kactus2 3.9.171 64bit Windows I have a file which misses the last port line but not in all cases. Screen capture from Kactus2 import window.  I have narrowed the...

Navigating components is very slow with 100s of ports.

4

Kactus2 3.9.171 64bit Windows It's slow at importing a large number of ports. Once they are imported, it is very slow at getting to the portmaps for the bus interface....

HW Component generate of VHDL does not use parameters for port signals.

1

The VHDL generate uses the value instead of the parameter equation for the port signal std_logic_vector. I think the Verilog works fine. I also might expect a generic section with...

Bus definition wire port import / export problem

1

Kactus2 3.9.171 64bit Windows If you export a wired port with master/slave pairs then they are not imported as a pair. One name is changed by adding a _0 suffix....

Component port export / import are not compatible. Ad-hoc import is always true.

2

Kactus2 3.9.171 64 Bit for Windows If I export the the ports as a csv file and them import it again, the Ad-hoc is always set to true. I tried...

[RP2] AP DHCP server ignores ifconfig IP and continues assigning 192.168.4.x subnet

2

### Port, board and/or hardware v1.25.0 RP2 on Pico W and Pico 2 W boards ### MicroPython version MicroPython v1.25.0 on 2025-04-15; Raspberry Pi Pico W with RP2040 MicroPython v1.25.0...