VHDL component import misses the last port.

[TonyReinberger]

Kactus2 3.9.171 64bit Windows

I have a file which misses the last port line but not in all cases.

Screen capture from Kactus2 import window.

I have narrowed the code down to the following

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
                            
entity DIG_TOP is

  port (
--    cfg_comp_12_analog_hyst_pos_in      : in  std_logic_vector(8-1 downto 0);
--    cfg_comp_12_analog_hyst_neg_in      : in  std_logic_vector(8-1 downto 0);
--    cfg_comp_13_analog_hyst_neg_in      : in  std_logic_vector(8-1 downto 0);
--    cfg_comp_14_analog_hyst_pos_in      : in  std_logic_vector(8-1 downto 0);
--    cfg_comp_14_analog_hyst_neg_in      : in  std_logic_vector(8-1 downto 0);
--    cfg_comp_15_analog_hyst_pos_in      : in  std_logic_vector(8-1 downto 0);
--    cfg_comp_15_analog_hyst_neg_in      : in  std_logic_vector(8-1 downto 0);
--    cfg_comp_16_analog_hyst_pos_in      : in  std_logic_vector(8-1 downto 0);

    -- clk, rstb
    clk_in	: in std_logic;
    rstb_in	: in std_logic
  );
end DIG_TOP;

If I remove any of the comment lines right after port( then the import works. There were additional comment lines that looked identical but it came down to just having these. I've tried taking the code from this issue to reproduce the problem and it does for me. Hopefully it is reproduced for you. Truly a bizarre bug.

Tony