HW Component generate of VHDL does not use parameters for port signals.

[TonyReinberger]

The VHDL generate uses the value instead of the parameter equation for the port signal std_logic_vector. I think the Verilog works fine.

I also might expect a generic section with the parameters and the default should probably be the value or value function. The verilog generate has the parameters but does not list the actual values or value function from the component.

Thanks,

Tony

[andrewandrepowell]

I was going to create an issue for this. It appears the VHDL generator does produce VHDL with the generic sections for both component and declarations. It would be nice to have support for that feature.