Implement support for AIA (Advanced Interrupt Architecture)

[Timmmm]

AIA (specification) adds a number of CSRs and widens some existing ones.

miselect and mireg are shared with the indirect CSR access extension Smcsrind, and provide a way to access IMSIC CSRs.

IMSIC is a hardware component associated with a single hart, that has its own CSRs eidelivery, eithreshold, eip0 etc. accessed via miselect/mireg. It also has a memory mapped region (similar to CLINT) for message-signalled interrupts.

IMSIC is optional so the first version of this could omit it, but I think eventually we want a model of this in Sail too.