Arjan Bink
Arjan Bink
In https://github.com/openhwgroup/cv32e40x/pull/440 'be' was replaced by 'size'. Maybe we will actually need both signals.
Introduce scoreboard. The following should be assured: - valid_0_i and xif_req in LSU cannot be asserted in the same cycle (prioritization should not be done in LSU as described in...
The following need to be updated in the RTL to match the User Manual: - mtvec: Make aligned to 128 bytes - mtvec: Update initial value according to new dependency...
We need an assertion (on the free running clock) checking the following: If core_sleep_o = 1, then the following should be 0: instr_req_o data_req_o fencei_flush_req_o compressed_valid issue_valid commit_valid mem_ready mem_result_valid...
The current RTL uses pending_single_step to signal a pending single step and it uses pending_debug for all other debug reasons. Also the pending_debug signal factors into the pending_single_step signal (see...
Coprocessor should implement Zmmul as a reference.
The debug request of the core is made sticky in two places it seems (i.e. in the debug module itself and in the core). That seems incorrect although the debug...
This task relates to finishing one of the known open items from https://github.com/openhwgroup/cv32e40x/pull/272: - Data hazards are ignored: If the result of an offloaded instruction is used by the subsequent...
This task relates to finishing one of the known open items from https://github.com/openhwgroup/cv32e40x/pull/272: - Synchronous exceptions within the coprocessor indicated by the result interface are ignored (they only inhibit writeback...
This issue is just about the register file implementation. The required hazard and bypass logic is out of scope for this issue. Currently only X_RFR_WIDTH == 32 is supported (see...