Update RTL according to User Manual - mtvec, mcause, etc.

[Silabs-ArjanB]

The following need to be updated in the RTL to match the User Manual:

• mtvec: Make aligned to 128 bytes
• mtvec: Update initial value according to new dependency on mtvec_addr_i
• mtvec: Make MODE a 2-bit WARL field with 0x0 as resolution value (SMCLIC = 0)
• mtvec: Make MODE a 2-bit WARL field with 0x3 as resolution value (SMCLIC = 1)
• mtvt: Make aligned to 2^(2+SMCLIC_ID_WIDTH) bytes
• mcause: Make exccode a 11-bit field
• tselect: Make WARL field with (DBG_NUM_TRIGGERS-1) as the value used when writing an illegal value.
• tdata1.type: Make WARL field with 0x6 as resolution value.
• mcontrol6.match: Make WARL field with 0x0 as resolution value
• Update NMI exception codes (store bus fault NMI (1025), load bus fault NMI (1024)
• (CV32E40S only) Update NMI exception codes (store parity/checksum fault NMI (1027), load parity/checksum fault NMI (1026)
• (CV32E40S only) Make mstatus.MPP a WARL field with 0x0 as resolution value

Note that the mtvec/mcause related changes require changes in if_stage, top level, etc. as well (check where these signals are used)

[Silabs-ArjanB]

Update rvfi_intr[10:3] in docs/user_manual/source/rvfi.rst and RVFI itself

[silabs-oysteink]

All bullets above should already be implemented as requested, with the following exceptions due to spec changes since the issue was created:

• mtvec.mode is WARL(0,1) instead of WARL(0*, 1) in CLINT mode (in line with user manual)
• tselect is WARL(0-DBG_NUM_TRIGGERS-1), not resolving to (DBG_NUM_TRIGGERS-1) but keeping old value
• tdata1.type is now WARL(2,5,6,15*)