Arjan Bink

Hi @eroom1966 >>Our assumption is that the CV32E40X is the 0.2.0, and the CV32E40X_DEV will be 0.4.0 as this is now the dev spec do you agree ? It is...

>>for the issue mentioned here >>mret in debug mode increments minstret (https://github.com/openhwgroup/cv32e40x/issues/558). >>Which cores does this apply to >>E40P, E40X, E40S Both cores. >> and also which version - is...

@eroom1966 I meant the CV32E40X and the CV32E40S only, not the CV32E40P.

> Item 3 is solved with PR #1307 @silabs-mateilga Which item 3? Can you indicate which of the CV32E40X and which of the CV32E40S items are still open?

> My assumption is that the design folks are going to maintain exactly as you describe: some type of tracing tools that provides a table of instructions executed, including an...

[CV32E40S_PMP-Arjan.xlsx](https://github.com/openhwgroup/core-v-verif/files/8812053/CV32E40S_PMP-Arjan.xlsx)

[CV32E40S_UserMode-Arjan.xlsx](https://github.com/openhwgroup/core-v-verif/files/8812069/CV32E40S_UserMode-Arjan.xlsx)

Hi @eroom1966 , please see the mentioned pull request: https://github.com/openhwgroup/cv32e40x/pull/491/files The PMP related CSRs only exists in the CV32E40S. They do not exist in the CV32E40X. The change was made...

@Imperas The changelist is autogenerated and can therefore contain comments that do not actually apply to the specific core itself. Such non-applicable content does not impact (and is not visible...

@eroom1966 Can this ticket be closed now?