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LLVM doesn't even disassemble it anymore. So I assume it solved upstream and it happens due to the RISCV module is outdated. ``` echo "0x15,0x93" | llvm-mc --triple=riscv64 --disassemble .text...

You can open a PR with your fix if you like. We will refactor the RISCV module soon though (hopefully done in a 2-3 months). So your effort might be...

Just checked. This is an issues with flawed generated LLVM tables. This makes the bug not really quickly fixable. Because we would need to generate the decoder tables again. This...

Related discussion: https://github.com/capstone-engine/capstone/discussions/2291

For most Auto-Sync architectures (see the table here: https://github.com/capstone-engine/capstone/issues/2015) you can add the `-r` flag to cstool to disassemble the instruction details of the "real" instruction. Here are the two...

btw, there is no option yet to also print the "real" instruction asm text (instead of the alias). But it isn't too complicated to implement this. It just isn't high...

The RISCV PR is a prototype. We will test if it performs better than the current module. Then either merge it into `next` or into an `experimental` branch (based on...

The LLVM disassembler essentially implements a state machine, checking bit fields and properties. So for a 32bit wide instruction it maybe checks (in practice) 2-5 fields within it to identify...

> Maybe need to construct a new Operand Class in the td file to fix this? Yeah, this would be the way. Also we would need to mark all `store`/`load`...

You can also add `supplement` information to the TriCore tables. Like [here](https://github.com/capstone-engine/llvm-capstone/blob/0162e010639835e25a3fe34846dd0741c4658736/llvm/utils/TableGen/PrinterCapstone.cpp#L2717-L2730). It assumes that there is only a single memory operand (hopefully true for TriCore) and the `mayStore`, `mayLoad`...