Rot127

Turns out this is not correct (checked an ISA post v7). It is just way more complicated (ARMv7 - ARM DDI 0406C.d):  

@gerph Did you get this instruction from a binary? Because it is marked as unpredictable/undefined (writes `spsr` but `mask` is 0).

Here an example of our IL (RzIL) and CFG for a binary of the Hexagon architecture: ```python ┌ int main(int argc, char **argv, char **envp); │ 0x00005110 ? allocframe(SP,#0x8):raw │...

> It seems that we only check the internal cs_insn, but not the text representation. We do not yet. It would be a good addition though: https://github.com/capstone-engine/capstone/issues/2740

fyi @jiegec In case you find time.

Ouh, sorry. I guess I forgot you added it and didn't tick the box in the Auto-Sync issue. Thanks!

Relevant discussion: https://github.com/capstone-engine/capstone/discussions/2290

For Alpha we used LLVM 3 as a basis. This means they likely haven't added those instructions when they deprecated the whole architecture. Are you aware of any other LLVM...

Those ones? ``` let isCall = 1, Ra = 23, Rb = 27, disp = 0, Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in def...

cc @trufae [To quote](https://github.com/capstone-engine/capstone/issues/2646#issuecomment-2772185552): > you can read more about this in the TI doc https://www.ti.com/lit/ug/spru732j/spru732j.pdf > > what re those details /without details disasm difference? i mean, the ||...