RV32 c.srli instruction with illegal shift amount is disassembled but should be custom extension space

[h01G3r]

Work environment

Questions	Answers
System Capstone runs on OS/arch/bits	Windows x86_64
Capstone module affected	riscv
Source of Capstone	git clone
Version/git commit	latest next, Commit 280b749

Instruction bytes giving faulty results

0x15, 0x93

Expected results

It should be:

Custom Extension / disassembly failed

Steps to get the wrong result

With cstool:

cstool -d riscv32 1593

or with Python

Additional Logs, screenshots, source code, configuration dump, ...

Instruction is disassembled as

 0  15 93        c.srli a4, 0x25
        ID: 128 (c.srli)
        op_count: 2
                operands[0].type: REG = a4
                operands[1].type: IMM = 0x25

        Groups: hasStdExtC

But according to https://lists.riscv.org/g/tech-unprivileged/attachment/536/0/unpriv-isa-asciidoc.pdf (p. 105) the shift value must not be greater than 31 (shamt[5], bit12 must be zero as shamt[5] == 1 is designated space for custom extensions in RISCV32.

[Rot127]

LLVM doesn't even disassemble it anymore. So I assume it solved upstream and it happens due to the RISCV module is outdated.

echo "0x15,0x93" | llvm-mc --triple=riscv64 --disassemble
	.text
<stdin>:1:1: warning: invalid instruction encoding
0x15,0x93
^

[h01G3r]

Locally, I manually patched the (autogenerated) disassembler-table. Would that be interesting for the project?

[Rot127]

You can open a PR with your fix if you like. We will refactor the RISCV module soon though (hopefully done in a 2-3 months). So your effort might be a little short lived.

[h01G3r]

I was aware of the Risc-V refactoring plans (just a manual patch of the decoder-table for that reason), but not about the timeline. For 2-3 month it might not make too much sense to put effort into the PR - since I had the change at hand anyhow, I opened one anyhow.