RickyTino

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icon company @hitwh-nscscc icon location Beijing, China icon location RTL Design / CPU(MIPS, RISC-V) / FPGA

Results 2 issues of RickyTino

About two-stage address translation under V mode

1 comment

Just to make sure, as I understand it, is it like a nested page walk? Which means for example, up to 24 memory accesses for Sv48.

[BUG] A '\t' is inserted unexpectedly when instantiating verilog modules

3 comment

**Describe the bug** Actually I am not quite sure if it is a bug or a feature. The plugin always insert a "\t" in front of the first signal connection...

bug