virtual-memory
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Published
20 hours ago •
riscv
riscv
About two-stage address translation under V mode
Just to make sure, as I understand it, is it like a nested page walk? Which means for example, up to 24 memory accesses for Sv48.
My understanding for two-stage address translation is shown in the picture above. I hope the spec can explain more detail about this, as a new developer who has no experience with x86/ARM address translation scheme would totally have no idea what a two-stage translation in RISC-V would be like.