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Published 20 hours ago • verified publisher icon mshr-h

[BUG] A '\t' is inserted unexpectedly when instantiating verilog modules

Open RickyTino opened this issue 6 months ago • 3 comments

Describe the bug Actually I am not quite sure if it is a bug or a feature. The plugin always insert a "\t" in front of the first signal connection when using the "module instantiation" provided by this plugin.

Environment (please complete the following information):

  • OS: Linux version 3.10.0-1160.105.1.el7.x86_64 ([email protected]) (gcc version 4.8.5 20150623 (Red Hat 4.8.5-44) (GCC) )
  • VS Code version 1.76.1
  • Extension version v1.11.3

Steps to reproduce Steps to reproduce the behavior:

  1. In certain source file press alt+i
  2. Select any SV module to instantiate
  3. See a tab '\t' appear in front of the first signal connection

Expected behavior No '\t' at all, or provide an option to set whether there be a '\t'

Actual behavior image

Additional context N/A

RickyTino avatar Aug 07 '24 08:08 RickyTino