Lofty
Lofty
YosysHQ/yosys#2272 adds a SystemVerilog output option. It would be nice to use it on vendor targets that support SV, but would require a Yosys version check. It might be best...
This is an RFC for #308. Some chips like the Intel Cyclone V SoC and Xilinx Zynq require `Instance`s to access certain I/O functions not directly available through top-level module...
If you have `x = Signal(decoder=Foo)` and try to do `x.match(Bar.QUUX)` or `m.Switch(x)`/`m.Case(Bar.QUUX)`, there should be an exception (`TypeError`?) thrown to catch any potential bugs where an enum of the...
So, here's my initial attempt at fixing #234 for powers of two by copy/pasting code for 32-bit math. I would like to generalise this to emit direct IR for all...
There has been a discussion this morning on Slack about the following simple question. Is RaptorJIT an implementation of Lua? Or is RaptorJIT an implementation of a language based on...
I got bitten by this optimisation not being present, resulting in the JIT emitting an unnecessary call to modulo.
This came up on IRC a while back, and I thought I'd write it down for the sake of posterity. Signals should have an optional `must_read` and `must_write` parameter for...
The recompiler should be modified/rewritten to use a single framework for all chips. This means more efficient use of maintenance time, because a backend for the framework ports all of...
more nextpnr-mistral things! --- I've talked about the LABsLogic Array Blocks a little bit before; they contain 10 ALMsAdaptive Logic Modules each, and are essentially the heart of the Intel...
this is a rough post on what I've tried doing to improve the performance of `nextpnr-mistral` on a specific benchmark: CoreScore. it might end up becoming a series, depending on...