Lofty

# Keep Calm and Carry On > Wow, it's been a while since I last wrote a blog article. Sorry about that. > Credit where credit is due: I learned...

# A Constructive Look At Pilkington's TS1 FPGA > In case somebody hasn't read [A Constructive Look At TempleOS](http://www.codersnotes.com/notes/a-constructive-look-at-templeos/) I really think you should. Did you know that Pilkington -...

My general goal for this blog is for fairly well-edited technical writing. This particular post isn't it - it's actually quite depressing - and you're welcome to ignore it if...

# LUT Mapping with Priority Cuts There's a disproportionately low number of people who know how to write a LUT mapper to people who depend on them for a living....

# LUT Mapping with Priority Cuts (II) > Some snippets are going to be in `diff` format, because I find that helps show the changes more. On the other hand,...

09/10/2020: FPGAs are Magic (II)

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# FPGAs Are Magic II ## More boilerplate (but we're getting somewhere!) The goal of *this* post is the FPGA-flow related boilerplate, as opposed to the ASIC-flow related boilerplate of...

25/09/2020: FPGAs are Magic (I).

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# FPGAs Are Magic I > Any sufficiently advanced technology is indistinguishable from magic. > - Arthur C. Clark FPGAs are *magic*. On my Twitter account, I have been posting...

cyclonev_clkena

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Presumably a clock-enable cell?

cyclonev_mac cell

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The Cyclone V has 18x18 bit multiplier cells, which Quartus calls `cyclonev_mac`. We should use them.

prussia_bios: Wrapping BIOS calls

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Some open questions: - Wrap _all_ syscalls? (Even the undocumented ones) - Wrap _useful_ syscalls? (Nobody cares about `_ExceptionEpilogue`, right?) - Implement it all in Rust? (as much as I'd...