veriloggen

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Slice in Wire with two dimension

1

Hi, I'm trying to do the following structure in Veriloggen: ``` m = Module('test') my_wire0 = m.Wire('my_wire0',8,2) my_wire1 = m.Output('my_wire1',2) my_wire1.assign(my_wire0[0][0:2]) print(m.to_verilog()) ``` But an exception is raised!

LucasBraganca

I do not think at the moment is possible to create `Seq` objects made out of combinational logic, in the same way that it is possible with sequential logic, as...

kiteloopdesign

Verilog output file has two empty lines before the `module` keyword ``` ('\n' '\n' 'module blinkled #\n' '(\n' ' parameter WIDTH = 8\n' ')\n' '(\n' ' input CLK,\n' ' input...

kiteloopdesign

I am using a python list comprehension to create on the fly the inputs ports for my module. `inputs = [m.Input (str(name), bw) for name,bw in ports_dict]` Where `ports_dict` is...

kiteloopdesign

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Explicit latency constraint between two stream objects which accesses to external resources outside of the stream.

1

thread.stream has some external operators to access outside of the stream pipeline, such as ToExtern/FromExtern, read_RAM, write_RAM. Additionally, RingBuffer and Scratchpad uses on-chip RAM as a random access buffer. The...

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Travis CI -> CircleCI?

4

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